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Description: 本程序的功能是实现串口通信,采用232传输协议,编码方式为8B/10B转换,即一位起始位,8位数据位,一位停止位,在actel Fusion系列开发板上得到验证,具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a start bit, 8 data bits, one stop bit.It has been verified in the development-board of actel Fusion Series , and is highly versatile.The programming language used in this module is verilog.
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Size: 2048 |
Author: 何斌 |
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Description: 232串口,我见过的最好的一个VERILOG描述的串口程序-232, one of the best I' ve ever seen description of the serial program VERILOG
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Size: 2584576 |
Author: wgy596 |
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Description: verilog/vhdl 串行口232通信程序-Spartan3E开发板调试通过-verilog/vhdl serial port communication program-Spartan3E 232 development board debugging
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Size: 1024 |
Author: xxit |
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Description: verilog 实现串口通信,其主要针对于uart异步232串口通信,经过硬件验证,其包含众多黑金开发板例程-verilog and uart
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Size: 12675072 |
Author: 黄明 |
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Description: 232串口源程序 verilog实现,频率可调 接受部分-RS232 verilog
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Size: 1024 |
Author: orca |
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Description: 232串口Verilog语言实现,可供新手参考编写,不太完善,需做补充。-Uart 232 Verilog
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Size: 1746944 |
Author: Qiushi |
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Description: uart串口发送控制模块 适合于485 422 232等接口-uart TXD——contrl Verilog
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Size: 1024 |
Author: 王长友 |
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Description: 该设计是基于 FPGA 的串口通信系统模拟仿真,通过对 RS-232 串行总线 接口的设计,掌握发送与接收电路的基本思路,并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述, 再将其整合为一个 RS-232 收发模块,最终在顶层模块中将两个 RS-232 模块例 化,实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication system based on FPGA)
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Size: 578560 |
Author: 小可大本
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Description: FPGA实现232通讯,用verilog语言(RS232 communication design in FPGA with verilog)
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Size: 2048 |
Author: gq_zhou
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